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Pipelining is an important technique used in several applications such as digital signal processing (DSP) systems, microprocessors, etc. It originates
Pipelining (DSP implementation)
Pipelining_(DSP_implementation)
Topics referred to by the same term
Pipelining may refer to: Pipeline (computing), aka a data pipeline, a set of data processing elements connected in series Protocol pipelining, a technique
Pipelining
technique of duplicating the functional blocks to increase the throughput of the DSP program in such a way that preserves its functional behavior at its outputs
Unfolding (DSP implementation)
Unfolding_(DSP_implementation)
parallel processing and pipelining techniques, it is better to choose parallel processing techniques with the following reasons Pipelining usually causes I/O
Parallel processing (DSP implementation)
Parallel_processing_(DSP_implementation)
transformation technique used in DSP architecture implementations for minimizing the number of functional blocks in synthesizing DSP architecture. Folding was
Folding_(DSP_implementation)
Topics referred to by the same term
predictable. Graphics pipeline, the method of rasterization-based rendering as supported by graphics hardware Pipelining (DSP implementation), a transformation
Pipeline_(disambiguation)
Specialized microprocessor optimized for digital signal processing
processor (DSP) is a specialized microprocessor chip, with its architecture optimized for the operational needs of digital signal processing. DSPs are fabricated
Digital_signal_processor
Method of improving instruction-level parallelism
engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every
Instruction_pipelining
Instruction slot being executed without the effects of a preceding instruction
instruction located immediately after a branch instruction on a RISC or DSP architecture; this instruction will execute even if the preceding branch
Delay_slot
Family of RISC-based computer architectures
link register). Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set
ARM_architecture_family
Series of Digital Signal Processor chips
processors (DSPs) from Texas Instruments. It was introduced on April 8, 1983, through the TMS32010 processor, which was then the fastest DSP on the market
TMS320
Computer architecture to aid parallelism
different substeps of sequential instructions simultaneously (termed pipelining), or even executing multiple instructions entirely simultaneously as in
Very_long_instruction_word
Microarchitecture designed by ARM Holdings
with deeply out of order, speculative issue 3-way superscalar execution pipeline DSP and NEON SIMD extensions are mandatory per core VFPv4 Floating Point
ARM_Cortex-A57
Component of computer engineering
modern Intel and AMD processors, are implemented with both microcode and pipelines. Improvements in pipelining and caching are the two major microarchitectural
Microarchitecture
Electrical Engineer and Computer Scientist (born 1959)
Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in Recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition"
Keshab_K._Parhi
Open source microprocessor
modified by any individual. The official implementation is maintained by developers at OpenCores.org. The implementation specifies a power management unit,
OpenRISC_1200
ARM microprocessor core model
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-A55
Instruction set architecture by Hitachi
added a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine
SuperH
Instruction set architecture
video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor
MIPS_architecture
Processors using some version of the MIPS architecture
high clock rates were achieved through the method of deep pipelining (called super-pipelining then). The improved R4400 followed in 1993. It had larger
MIPS_architecture_processors
Microprocessor with more than one processing unit
(DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation
Multi-core_processor
Type of arithmetic where output is limited to a fixed range of values
result can be a catastrophic loss in signal-to-noise ratio in a DSP system. Signals in DSP designs are therefore usually either scaled appropriately to avoid
Saturation_arithmetic
Central processing unit
90% greater performance. Pipelined processor with deeply out-of-order, speculative issue 3-way superscalar execution pipeline DSP and NEON SIMD extensions
ARM_Cortex-A72
Micro-electronic component
scheduling algorithms. Hardware and software tasks are often pipelined in processor design. Pipelining is an important principle for speedup in computer architecture
System_on_a_chip
Group of 32-bit RISC processor cores
integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP)
ARM_Cortex-M
Hardware cache of a central processing unit
the MIPS R6000 uses this cache type as the sole known implementation. The R6000 is implemented in emitter-coupled logic, which is an extremely fast technology
CPU_cache
Combinational digital circuit
to accelerate complex operations. In such systems, the ALUs are often pipelined, with intermediate results passing through ALUs arranged like a factory
Arithmetic_logic_unit
Components from image source to output
consisting of two or more separate processing blocks. An image/video pipeline may be implemented as computer software, in a digital signal processor, on an FPGA
Color_image_pipeline
Digital circuit that produces sums from inputs
can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. The most common implementation is with:
Adder_(electronics)
Digital processing technique
Parallel multidimensional digital signal processing (mD-DSP) is defined as the application of parallel programming and multiprocessing to digital signal
Parallel multidimensional digital signal processing
Parallel_multidimensional_digital_signal_processing
Model that describes the programmable interface of a computer processor
machine code running on an implementation of that ISA in a fashion that does not depend on the characteristics of that implementation, providing binary compatibility
Instruction_set_architecture
extensions that greatly improved performance for digital signal processing (DSP) algorithms. Jonah, Probell (2012). "lexra". www.probell.com. Retrieved 2021-12-02
Lexra
2012 computer chip design
property and processor designs. 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline DSP and NEON SIMD extensions are mandatory
ARM_Cortex-A53
Processor executing one instruction in minimal clock cycles
Novick, Greg; Shimano, Kirk. "Pipelining". RISC Architecture. Flynn, Michael J. (1995). Computer Architecture: Pipelined and Parallel Processor Design
Reduced instruction set computer
Reduced_instruction_set_computer
Family of microprocessor cores with ARM microarchitecture
Analog Devices ADSP-SC57x, ADSP-SC58x series ARM Cortex-A5 + SHARC+ multicore DSP Atmel SAMA5Dxx Freescale Vybrid Series NTC Module 1879VM8Ya (penta-core Cortex-A5
ARM_Cortex-A5
Microprocessor
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-A75
Security-related instruction code processor extension
that claims to have superior performance with the elimination of the implementation complexity of other proposed solutions. The LSDS group at Imperial College
Software_Guard_Extensions
64 bit ARMv8 architecture processor
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-A73
Processor design concept
specifies a software-managed TLB. The SPARC V9 architecture allows an implementation of SPARC V9 to have no MMU, an MMU with a software-managed TLB, or an
Translation_lookaside_buffer
Microprocessor developed by Sun Microsystems
improvement. The process was perfected on TI's MVP digital signal processor (DSP) with some features missing such as three levels of metal instead of four
UltraSPARC
Semiconductor company
collaboration with Samsung a 1 GHz implementation of the ARM Cortex-A8 chip; it had developed a similar high-speed implementation of the Cortex-R4 chip two years
Intrinsity
Family of microprocessor cores with ARM microarchitecture
its ARM9EJ sibling, implement the basic ARM9TDMI pipeline, but add support for the ARMv5TE architecture, which includes some DSP-esque instruction set
ARM9
32-bit RISC microcontroller architecture
on-chip peripherals and general purpose I/Os and fixed point DSP arithmetic. Both implementations can be combined with a compatible set of peripheral controllers
AVR32
Task of creating a processor
lessen the implementation burden by acquiring some of these items by purchasing them as intellectual property. Control logic implementation techniques
Processor_design
Microprocessor core model by ARM
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-A78
C++ framework for compiler development
across CPUs, GPUs, and accelerators, DSP-MLIR, a compiler infrastructure tailored for digital signal processing (DSP) applications, and torch-mlir, which
MLIR_(software)
and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. Keil also provides a somewhat newer summary
List_of_ARM_processors
Type of digital adder
addition of more than two binary numbers after multiplication. A big adder implemented using this technique will usually be much faster than conventional addition
Carry-save_adder
Emulator and media player frontend
Peer-to-peer netplay that uses a rollback technique similar to GGPO; Audio DSP plugins like an equalizer, reverb and other effects; Advanced savestate features –
RetroArch
Type of program in computer graphics
accelerators (such as graphics processing units (GPUs), digital signal processors (DSPs), or field-programmable gate arrays (FPGAs)), separate from but used by a
Shader
Algorithm for computing trigonometric, hyperbolic, logarithmic and exponential functions
CORDIC math implementation CORDIC implementation in verilog CORDIC Vectoring with Arbitrary Target Value Python CORDIC implementation Archived 2017-03-17
CORDIC
Open-source CPU instruction set architecture
The cores in PULPino implement a simple RV32IMC ISA for microcontrollers (Zero-Riscy) or a more powerful RV32IMFC ISA with custom DSP extensions for embedded
RISC-V
Use of a GPU for computations typically assigned to CPUs
and sound effects processing, to use a GPU for digital signal processing (DSP) Analog signal processing Speech processing Digital image processing Video
General-purpose computing on graphics processing units
General-purpose_computing_on_graphics_processing_units
Serial interface for testing integrated circuits
its DSP and micro products. Such tools tend to be highly featured and may be the only real option for highly specialized chips like FPGAs and DSPs. Lower-end
JTAG
Single chip microcontroller series by Intel
remain popular today. Some derivatives integrate a digital signal processor (DSP) or a floating-point unit (coprocessor, FPU). Beyond these physical devices
Intel_MCS-51
32-bit ARM core
and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10
ARM11
Register in a computer's CPU
being transferred to and from the immediate access storage. It was first implemented in von Neumann model. It contains a copy of the value in the memory location
Memory_buffer_register
Application programming interface for multimedia playback
used in Media Foundation primarily to implement decoders, encoders, mixers and digital signal processors (DSPs) – between media sources and media sinks
Media_Foundation
Central processing unit by Sony Computer Entertainment and Toshiba
and VPU1. These were essentially DSPs tailored for 3D math, and the forerunner to hardware vertex shader pipelines. Each VPU features 32 128-bit vector
Emotion_Engine
CPU instruction set
been added. These instructions can be used to speed up the implementation of a number of DSP and 3D operations. There is also a new instruction to convert
SSE3
Microprocessor core model
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-A77
Circuit that performs subtraction
B_{i+1}=X_{i}<(Y_{i}+B_{i})} , where ⊕ represents exclusive or. Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's
Subtractor
Computer programming paradigm
short stream effect. Pipelining is a very widespread and heavily used practice on stream processors, with GPUs featuring pipelines exceeding 200 stages
Stream_processing
CPU released in 2018
components such as graphics processing units (GPUs), digital signal processors (DSPs), and image signal processors (ISPs) on a single chip. The Cortex-A76 first
ARM_Cortex-A76
Family of microprocessor cores with ARM microarchitecture
licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz
ARM_Cortex-A15
Processor architecture
range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable
Nios_II
Additional storage that enables faster access to main storage
brings the total 'number of caches (levels+functions) to 6. "qualcom Hexagon DSP SDK overview". Archived from the original on 1 November 2019. Retrieved 10
Cache_(computing)
order to develop a reference implementation known as Escalante. Samsung and 3DO were working together to design a single-chip DSP-like "Media Signal Processor"
Microsoft_Talisman
Aspect of the instruction set architecture of CPUs
19, Pipelining Data Forwarding". CS411 Selected Lecture Notes. "High Performance Computing, Notes of Class 11 (Sept. 15 and 20, 2000) - Pipelining". Archived
Addressing_mode
Microprocessor core model by ARM
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-X1
Ongoing armed conflict in South Asia
killed in a militant attack in Wana while six police personnel including a DSP were killed and three were wounded in an insurgent ambush in Kohat District
2026_Afghanistan–Pakistan_war
Higher level of microcode
Millicode routines are used to implement more complex instructions visible to the user of the system. Implementation of millicode may require a special
Millicode
Microprocessor series by AMD
K6-III+ had the "Enhanced 3DNow!"(Extended 3DNow! or 3DNow+) which added 5 new DSP instructions, but not the 19 new extended MMX instructions. The original
AMD_K6-III
Family of microprocessor cores with ARM microarchitecture
suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC)
ARM_Cortex-A34
Nikon media processors
display interfaces and other modules are added and a digital signal processor (DSP) increases the number of simultaneous computations. On-chip 32-bit microcontroller
Expeed
still present. An Action Hero In a mid-credits scene, "Jehda Nasha" is sung. DSP A collection of outtakes, behind the scenes and during the end credits. The
List of films with post-credits scenes
List_of_films_with_post-credits_scenes
Type of parallel processing
vector-float units could function as an autonomous digital signal processor (DSP) executing its own instruction stream, or as a coprocessor driven by ordinary
Single instruction, multiple data
Single_instruction,_multiple_data
Chinese semiconductor company
revision 2 instruction set. It implements an 8-stage pipeline XBurst CPU technology consists of 2 parts: A RISC/SIMD/DSP hybrid instruction set architecture
Ingenic_Semiconductor
Low-level programming language family
Magnus; Tyson, Gary (2013). "Improving processor efficiency by statically pipelining instructions". Proceedings of the 14th ACM SIGPLAN/SIGBED conference on
Assembly_language
Sound card
high-quality 64-voice MIDI sample-based synthesizer and an integrated FX8010 DSP chip for real-time digital audio effects. A major design change from the
Sound_Blaster_Live!
Computer operating system
and others. In its later versions, Helios was ported to the TI TMS320C40 DSP and to the ARM architecture, the latter used by the Active Book tablet device
Helios_(operating_system)
Specialized computer language used to describe electronic circuits
2012-08-11. "Digital Signal Processing (DSP) Builder - Intel® FPGAs". Intel. Retrieved 2021-09-20. "System Generator for DSP". Xilinx.com. Archived from the original
Hardware_description_language
Type of computer processor
a command list. The PlayStation 2's Emotion Engine contained an unusual DSP-like SIMD vector unit capable of both modes of operation. To make the best
Coprocessor
32 bit microprocessor made by Apollo Computer
entered production. Andrews, Warren (1 May 1989). "Distinctions blur between DSP solutions". Computer Design. pp. 86–89, 92–94, 96–99. Retrieved 6 July 2025
Apollo_PRISM
Computing technique used to achieve parallelism
such as pipelining and the use of multiple parallel functional units, are used for maximum single CPU speed. MPI is commonly used to implement SPMD. As
Single_program,_multiple_data
Microprocessor
for improving the performance of fixed-point digital signal processing (DSP) applications. A lower cost version of the R4650, the R4640, was announced
R4600
Series of graphics processing units
September 2020. "Qualcomm Snapdragon 855: An overview of its CPU, GPU, ISP, and DSP". xda-developers. 5 December 2018. Retrieved 5 December 2018. Frumusanu,
Adreno
Computer system with a dedicated function
standard class of dedicated processors is the digital signal processor (DSP). Since the embedded system is dedicated to specific tasks, design engineers
Embedded_system
Information assurance (IA) requirements overview
Both DSPs and OES are now held accountable for reporting major security incidents to Computer Security Incident Response Teams (CSIRT). While DSPs are
Cyber-security_regulation
Multimedia framework
Instruments SoCs is also accessible through GStreamer: gst-dmai, gst-openmax, gst-dsp. VDPAU and VAAPI are supported with GNOME Videos >= 2.28.0 and GStreamer
GStreamer
Family of processor cores
FPU that handles DSP instructions. Emitting 1.6 W at 1.6 GHz on a 45 nm fabrication process. The 9 stage out of order, 5-issue pipeline handles speeds up
PowerPC_400
Software platform for collecting and managing data
and segmented, it is put into use in the marketplace through servers or DSPs. From here, advertisers uses other third-party services to access a DMP and
Data_management_platform
Small computer on a single integrated circuit
roles, where they may need to act more like a digital signal processor (DSP), with higher clock speeds and power consumption. The first multi-chip microprocessors
Microcontroller
President of Turkey since 2014
Prime Minister Kostas Karamanlis inaugurated the Greek-Turkish natural gas pipeline giving Caspian gas its first direct Western outlet. Turkey and Greece signed
Recep_Tayyip_Erdoğan
Package of financial transaction taxes
Transaction Taxes: The International Experience and the Lessons for Canada. http://dsp-psd.tpsgc.gc.ca/Collection-R/LoPBdP/BP/bp419-e.htm EUROBAROMETER 74 – ECONOMIC
Robin_Hood_tax
Digital signal sample rate converter
Understanding cascaded integrator–comb filters An Intuitive Look at Moving Average and CIC Filters Cascaded Integrator Comb (CIC) Filters – A Staircase of DSP
Cascaded integrator–comb filter
Cascaded_integrator–comb_filter
Electronic circuit used to multiply binary numbers
single-cycle multiply–accumulate unit often used up most of the chip area of early DSPs. The method taught in school for multiplying decimal numbers is based on
Binary_multiplier
Microarchitecture by Nvidia
in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc
Project_Denver
Chinese fabless semiconductor manufacturing company, fully owned by Huawei
05 GHz) and a 22-core Mali-G78 GPU with Kirin Gaming+ 3.0 implementation. The integrated quad pipeline NPU (Dual Big Core + 1 Tiny Core configuration) is equipped
HiSilicon
Type of computer memory
2020-03-24. Retrieved 2020-03-24. Shared Memory Interface with the TMS320C54x DSP (PDF), archived (PDF) from the original on 2019-05-04, retrieved 2019-05-04
Static_random-access_memory
PIPELINING DSP-IMPLEMENTATION
PIPELINING DSP-IMPLEMENTATION
Female
Finnish
Finnish form of Russian Kseniya, SENJA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)."
Surname or Lastname
Swedish
Swedish : ornamental name from asp ‘aspen tree’.Norwegian : habitational name from a farmstead named with asp ‘aspen tree’.German and English : topographic name from Middle High German aspe, Middle English aspe ‘aspen tree’.English : habitational name from a minor place named with Old English æspe, æpse ‘aspen tree’ (see Apps).
Girl/Female
Tamil
A lamp, Beautiful
Female
Slovene
 Croatian and Slovene form of Greek Xenia, KSENIJA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)." Compare with other forms of Ksenija.
Female
Greek
(ΖÎνα) Contracted form of Greek Zenia, ZENA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)."
Boy/Male
Basque, French, German, Portuguese
Baptist; To Dip
Surname or Lastname
Irish (County Donegal)
Irish (County Donegal) : Anglicized form of Gaelic Ó Duibhidhir or sometimes of Mac Duibhidhir (see Dwyer, also Dyer).English : of uncertain derivation; possibly from diver, an agent derivative of Middle English dive ‘to dip or plunge’, but if so the application is obscure. It may be a nickname for someone compared to a diving bird. Compare Ducker.
Boy/Male
Bengali, Indian
Candle
Surname or Lastname
Norwegian
Norwegian : habitational name from a place named Aspen, from an inflected form of asp ‘aspen tree’.English : topographic name for someone living by an aspen tree.
Female
Russian
(КÑениÑ) Russian form of Greek Xenia, KSENIJA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)." Compare with other forms of Ksenija.
Boy/Male
British, Christian, Dutch, English, French, German, Irish
To Dip; Baptist
Female
Polish
Polish form of Greek Xenia, KSENIA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)."
Girl/Female
Hindu, Indian
The Sweet Smell of a Pack of Fun-dip Mixed with a New Flame
Surname or Lastname
English
English : habitational name from Dimsdale, a place in Staffordshire, possibly named from Middle English dimple ‘dip in the ground’ + dale ‘valley’.
Girl/Female
Indian
A lamp, Beautiful
Female
Greek
(ΖÎνια) Variant spelling of Greek Xenia, ZENIA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)."
Female
Russian
(ÐкÑиÌниÑ) Variant spelling of Russian Ksenija, AKSINYA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)."
Male
Japanese
(1-信, 2-延) Japanese name NOBU means 1) "faith" or 2) "to extend, prolong (esp. words)."
Female
Hungarian
Hungarian form of Greek Xenia, XÉNIA means "stranger, foreigner," but sometimes rendered "hospitable (esp. to foreigners)."
Girl/Female
Hindu, Indian
Small Light Like Candle; Small Lamp
PIPELINING DSP-IMPLEMENTATION
PIPELINING DSP-IMPLEMENTATION
Boy/Male
Arabic, Muslim
Allah's Messenger; Pure
Girl/Female
Biblical
Good, goodness.
Boy/Male
Indian
Beutifull
Girl/Female
Hindu, Indian, Tamil
Truth Loving
Boy/Male
African, Australian, Swahili
Lynx; Panther; From Kikuyu
Boy/Male
Hindu, Indian, Muslim
Powerful; Mighty; Strong; Rich; Successful
Surname or Lastname
English
English : perhaps a variant of Crossland.
Boy/Male
Indian, Sanskrit
Sound; Noise; Roar; Reality
Boy/Male
British, English
Bright Friend
Boy/Male
Hebrew
God sees.
PIPELINING DSP-IMPLEMENTATION
PIPELINING DSP-IMPLEMENTATION
PIPELINING DSP-IMPLEMENTATION
PIPELINING DSP-IMPLEMENTATION
PIPELINING DSP-IMPLEMENTATION
v. i.
To perform the action of plunging some receptacle, as a dipper, ladle. etc.; into a liquid or a soft substance and removing a part.
v. i.
To dip snuff.
v. i.
To incline downward from the plane of the horizon; as, strata of rock dip.
v. i.
To dip.
v. i.
To enter slightly or cursorily; to engage one's self desultorily or by the way; to partake limitedly; -- followed by in or into.
n.
A small, hooded, poisonous serpent of Egypt and adjacent countries, whose bite is often fatal. It is the Naja haje. The name is also applied to other poisonous serpents, esp. to Vipera aspis of southern Europe. See Haje.
v. i.
To immerse one's self; to become plunged in a liquid; to sink.
v. t.
To plunge or engage thoroughly in any affair.
n.
The action of dipping or plunging for a moment into a liquid.
v. t.
To open; as, to dup the door.
v. t.
To engage as a pledge; to mortgage.
n.
Alt. of Doop
v. i.
To drop the bait gently on the surface of the water.
n.
Inclination downward; direction below a horizontal line; slope; pitch.
v. t.
To take out, by dipping a dipper, ladle, or other receptacle, into a fluid and removing a part; -- often with out; as, to dip water from a boiler; to dip out water.
n.
A dip; a low courtesy.
n.
A dipped candle.
n.
A liquid, as a sauce or gravy, served at table with a ladle or spoon.
v. i.
To pierce; to penetrate; -- followed by in or into.