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Topics referred to by the same term
MMX may refer to: 2010, in Roman numerals MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel MMX Mineração, a
MMX
Instruction set designed by Intel
MMX is a single instruction, multiple data (SIMD) instruction set architecture extension* designed by Intel, introduced on January 8, 1997 with its Pentium
MMX_(instruction_set)
Planned sample-return mission by Japan to Phobos
Martian Moons eXploration (MMX) is a robotic space probe set for launch in 2026 to bring back the first samples from Mars' largest moon Phobos. Developed
Martian_Moons_eXploration
Extended MMX refers to one of two possible extensions to the MMX instruction set for x86. Included in Intel's Streaming SIMD Extensions were a number
Extended_MMX
Intel microprocessor
January 1997, the Pentium MMX was released, complementing the same basic microarchitecture of the original Pentium with the MMX instruction set, larger
Pentium_(original)
from Intel. Processors branded Pentium Processor with MMX Technology (and referred to as Pentium MMX for brevity) are also listed here. It was replaced by
List of Intel Pentium processors
List_of_Intel_Pentium_processors
Core 3, Core 5, Core 7, and Core 9 branded processors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel
List of Intel Core desktop processors
List_of_Intel_Core_desktop_processors
Intel SIMD processor supplementary instruction sets introduced by Intel
instructions implement the integer vector operations also found in MMX. Instead of the MMX registers they use the XMM registers, which are wider and allow
SSE2
transistor count for post-Diamondville Atom microprocessors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Hyper-Threading
List_of_Intel_Atom_processors
MMX is the mining company of the EBX Group founded in 2005. It is engaged in the extraction, beneficiation and sale of iron ore and minerals in Brazil
MMX_Mineração
Computer chip instruction set extension
and graphics processing. Intel's first IA-32 SIMD effort was the MMX instruction set. MMX had two main problems: it re-used existing x87 floating-point registers
Streaming_SIMD_Extensions
consists of: MMX, SSE, SSE2, Enhanced 3DNow!, NX bit MMX, SSE, SSE2, Enhanced 3DNow!, NX bit MMX, SSE, SSE2, Enhanced 3DNow!, NX bit MMX, SSE, SSE2, Enhanced
List_of_AMD_mobile_processors
Family of instruction set architectures
virtual addresses. MMX is a SIMD instruction set designed by Intel and introduced in 1997 for the Pentium MMX microprocessor. The MMX instruction set was
X86
Intel microprocessor
the P6 microarchitecture seen on the Pentium Pro with the MMX instruction set of the Pentium MMX, and is the second major generation of the Pentium, succeeding
Pentium_II
Martian moons lander
Moons eXploration (MMX) mission to Phobos, a moon of Mars. The rover is designed to land on Phobos and explore its surface before the MMX spacecraft lands
Idefix_(rover)
MMX Steppings: A0, A1, B0 All models support: MMX L2 cache is on-die, running at full CPU speed All models support: MMX, SSE All models support: MMX,
List of Intel Celeron processors
List_of_Intel_Celeron_processors
Internet top-level domain
Registry Completes $30.6M Sale to MMX". Faegre Drinker Biddle & Reath LLP. July 2018. Retrieved 23 June 2026. "MMX Announces Acquisition of ICM Registry"
.xxx
support: MMX, SSE, Enhanced 3DNow! CPU-ID: 6-8-0 (A), 6-8-1 (B) All models support: MMX, SSE, Enhanced 3DNow! CPU-ID: 6-A-0 All models support: MMX, SSE,
List of AMD Athlon XP processors
List_of_AMD_Athlon_XP_processors
Chip harvests from Conroe with half L2 cache disabled All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Intel
List of Intel Xeon processors (Core-based)
List_of_Intel_Xeon_processors_(Core-based)
kb (data + instruction) L2 cache: 1024 kb (full speed) Instruction sets: MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 Models: FX-51 (2.2 GHz) and FX-53
List_of_AMD_FX_processors
higher TDP than a standard Opteron. APU features table All models support: MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 All models with OPN ending in
List of AMD Opteron processors
List_of_AMD_Opteron_processors
per core L2 cache: 512 KB on dual-core, 1 MB on tri- and quad-core models MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, Cool'n'Quiet
List of AMD processors with 3D graphics
List_of_AMD_processors_with_3D_graphics
MMX Open Art Venue was an art gallery in Berlin, founded in 2010 as a one-year art experiment and reincarnated as re:MMX in 2012. The MMX project, which
MMX_Open_Art_Venue
(Steppings, Process) All models support: MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet All models support: MMX, SSE, SSE2, Enhanced 3DNow!, NX bit
List of AMD Athlon 64 processors
List_of_AMD_Athlon_64_processors
support: MMX, SSE, SSE2 Transistors: 42 million Die size: 217 mm2 Steppings: B2, C1, D0, E0 Intel Family 15 Model 2 All models support: MMX, SSE, SSE2
List of Intel Pentium 4 processors
List_of_Intel_Pentium_4_processors
Calendar year
2010 (MMX) was a common year starting on Friday of the Gregorian calendar, the 2010th year of the Common Era (CE) and Anno Domini (AD) designations, the
2010
W for single core chips or 25 W for dual core chips. All models support: MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet
List_of_AMD_Phenom_processors
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)
List of Intel Xeon processors (Broadwell-based)
List_of_Intel_Xeon_processors_(Broadwell-based)
All models support: MMX, SSE, Enhanced 3DNow! All models support: MMX, SSE, Enhanced 3DNow! All models support: MMX, Extended MMX, SSE, 3DNow!, Enhanced
List of AMD Sempron processors
List_of_AMD_Sempron_processors
targeted at the consumer market. 9.5 million transistors All models support: MMX, SSE The 'B' suffix denotes a 133 MHz FSB The '80525PYxxx512' number denotes
List of Intel Pentium III processors
List_of_Intel_Pentium_III_processors
Microprocessor microarchitecture by AMD
controller: dual channel DDR2-1066 MHz with unganging option ISA extensions: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, AMD64, NX bit, AMD-V Power
AMD_10h
computing market. All models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow! All models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow
List_of_AMD_Turion_processors
support: MMX All models support: MMX All models support: MMX, 3DNow! All models support: MMX, 3DNow! All models support: MMX All models support: MMX, 3DNow
List_of_AMD_K6_processors
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, F16C, BMI1 (Bit Manipulation Instructions1), BMI2, Enhanced Intel SpeedStep
List of Intel Xeon processors (Haswell-based)
List_of_Intel_Xeon_processors_(Haswell-based)
Brand of discontinued microprocessors produced by Intel
Xeon respectively. The Pentium II line added the MMX instructions that were also present in the Pentium MMX. Versions of these processors for the laptop market
Pentium
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)
List of Intel Xeon processors (Sandy Bridge–based)
List_of_Intel_Xeon_processors_(Sandy_Bridge–based)
2010 single by Enigma
"MMX (The Social Song)" is a single by the band Enigma released on 15 December 2010 to celebrate the 20th anniversary of the musical project. In October
MMX_(The_Social_Song)
Brazilian businessman (born 1956)
These five companies were: OGX (oil and gas), MPX (energy), LLX (logistics), MMX (mining), and OSX (offshore services and equipment). Nowadays, EBX advises
Eike_Batista
Marketing name by AMD
L1-Cache: 64 + 64 KiB (Data + Instructions) L2-Cache: 256 KiB, full speed MMX, 3DNow!, SSE Socket A (EV6) Front side bus: 166 MHz (FSB 333) VCore: 1.6
Sempron
Extension to the x86 instruction set by AMD
MMX instructions. The new 3DNow! instructions were added to boost DSP. The new MMX instructions were added to boost streaming media. The 19 new MMX instructions
3DNow!
extensions. These extensions, starting from the MMX instruction set extension introduced with Pentium MMX in 1997, typically define sets of wide registers
List_of_x86_SIMD_instructions
embedded market. All models support: MMX, 3DNow! All models support: MMX, SSE, VIA PadLock (AES, RNG) All models support: MMX, SSE, VIA PadLock (AES, RNG) VIA
List of VIA Eden microprocessors
List_of_VIA_Eden_microprocessors
English neo-prog band
Despite horrendous technical problems, the band were extremely well received. MMX, a new live double DVD and CD, was released in November 2010 and represents
Twelfth_Night_(band)
Microprocessor developed by Intel
were replaced by Pentium OverDrive MMX, which also upgraded the Pentium 120 - 200 MHz to the faster version with MMX technology. PODPMT60X150: up to 150 MHz
Pentium_OverDrive
designation. All models support: MMX, Enhanced 3DNow! L2 cache always runs with full CPU speed All models support: MMX, Enhanced 3DNow! Platform "Virgo"
List_of_AMD_Athlon_processors
All models support: MMX, Enhanced 3DNow! All models support: MMX, SSE, Enhanced 3DNow! All models support: MMX, Extended MMX, SSE, 3DNow!, Enhanced 3DNow
List_of_AMD_Duron_processors
3–, Core 5–, Core 7–, and Core 9–branded processors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel
List of Intel Core mobile processors
List_of_Intel_Core_mobile_processors
Discography of English rock band Procol Harum
February 2010 Label: Salvo/BMG Formats: digital download — — — — — — — — — MMX Released: July 2012 Label: Salvo/BMG Formats: digital download — — — — —
Procol_Harum_discography
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX2, AVX-512, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
List of Intel Xeon processors (Skylake-based)
List_of_Intel_Xeon_processors_(Skylake-based)
Multimedia library for C
designed to leverage VIS on SPARC processors and later added support for MMX/SSE/SSE2 on Intel/AMD processors. Since mediaLib is written in C and SIMD
MediaLib
MMX, 3DNow!, LongHaul FPU runs at 50% of core speed All models support: MMX, 3DNow!, LongHaul FPU runs at 50% of core speed All models support: MMX,
List of VIA C3 microprocessors
List_of_VIA_C3_microprocessors
Computer microprocessor
processor included a feedback dynamic instruction reordering mechanism, MMX instructions, and a floating-point unit (FPU). It was also made pin-compatible
AMD_K6
Series of CPUs by AMD
(data + instructions), per core L2 cache: 256, 512 KB full speed, per core MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX Bit Socket 939
Athlon_64_X2
Series of CPUs by AMD
Common among the Athlon 64 line are a variety of instruction sets including MMX, 3DNow!, SSE, SSE2, and SSE3. All Athlon 64s also support the NX bit, a security
Athlon_64
Discontinued line of business laptops
lines and white 7300 and 7700 high-end lines with Pentium I (or Pentium MMX) CPU's. Second gen — the design unification: new 1500/1700 and 3500 models
Compaq_Armada
support: MMX L2 cache is off-die and runs at 50% CPU speed Part numbers prefixed with a B are for boxed retail CPUs All models support: MMX L2 cache is
List of Intel Pentium II processors
List_of_Intel_Pentium_II_processors
Series of CPUs
the simple in-order execution pipeline of its predecessor, but added dual MMX/3DNow! processing units that could operate in superscalar execution. This
WinChip
German research center for aerospace and power engineering
within and outside the Solar System, such as the Martian Moons eXploration (MMX) mission to Mars's moon Phobos – a German-French-Japanese collaboration.
German_Aerospace_Center
Series of CPUs by AMD
cache: 64 + 64 KB (Data + Instructions) L2 cache: 64 KB, full speed MMX, Extended MMX, 3DNow!, Extended 3DNow! Socket A (EV6) Front-side bus: 100 MHz (200
Duron
German metalcore band
released four full-lengths; Transmetropolitan (2007), In Shoals (2009) and MMX (2010). The group's final album Voyeur (2012) was launched just one year
War_from_a_Harlots_Mouth
M7 microprocessor. VIS is not an instruction toolkit like Intel's MMX and SSE. MMX has only 8 registers shared with the FPU stack, while SPARC processors
Visual_Instruction_Set
workstations All models except X3430 support Hyper-Threading All models support: MMX, XD bit, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Intel 64, SpeedStep, Turbo
List of Intel Xeon processors (Nehalem-based)
List_of_Intel_Xeon_processors_(Nehalem-based)
is a list of Ivy Bridge–based Intel Xeon processors. All models support: MMX, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Advanced
List of Intel Xeon processors (Ivy Bridge–based)
List_of_Intel_Xeon_processors_(Ivy_Bridge–based)
Xeon processors. Based on NetBurst microarchitecture All models support: MMX, SSE, SSE2 All models support dual-processor configurations Die size: 241
List of Intel Xeon processors (NetBurst-based)
List_of_Intel_Xeon_processors_(NetBurst-based)
Brazilian conglomerate
comprises six companies listed in B3's Novo Mercado, including Dommo Energia, MMX, OSX, and CCX. It was founded by Brazilian businessman Eike Batista, who
EBX_Group
harvests from Thuban with two cores and L3 cache disabled All models support: MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet
List of AMD Athlon II processors
List_of_AMD_Athlon_II_processors
Instruction for x86 microprocessors
can use the CPUID to determine processor type and whether features such as MMX/SSE are implemented. Prior to the general availability of the CPUID instruction
CPUID
Personal computer series released in 1994
processors during its lifetime, the Pentium MMX, Pentium II and Pentium III. Models using the Pentium MMX came in speeds of 166, 200 and 233 MHz; models
IBM_PC_Series
processor. All models support: MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet, AMD-V All models support: MMX, SSE, SSE2, SSE3, Enhanced
List of AMD Athlon X2 processors
List_of_AMD_Athlon_X2_processors
as well as Pentium Extreme Edition 840, 955, and 965. All models support: MMX, SSE, SSE2, SSE3, Intel 64, XD bit (an NX bit implementation) Enhanced Intel
List of Intel Pentium D processors
List_of_Intel_Pentium_D_processors
Parallel processing technique
well-known example of a SWAR architecture was the Intel Pentium with MMX, which implemented the MMX extension set. The Intel Pentium, by contrast, did not include
SWAR
spacecraft. On 20 October, JAXA plans to launch the Martian Moons eXploration (MMX) mission to the moons of Mars with the aim of bringing back the first samples
2026_in_spaceflight
Airport in Sweden
Malmö Airport (IATA: MMX, ICAO: ESMS) is an international airport located in Scania, Sweden, approximately 28 kilometres (17 mi) east of Malmö. It is
Malmö_Airport
(IATA: BGY) and Parma Airport (IATA: PMF). ^2 MMA covers Malmö Airport (IATA: MMX) only. ^3 MOW is common IATA code for Domodedovo International Airport (IATA:
List of airports by IATA code: M
List_of_airports_by_IATA_code:_M
Upcoming microprocessor family by Intel
Wolf (E-cores) Instruction set x86-64 Instructions IA-32, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.2, APX, AES-NI
Nova_Lake_(microprocessor)
Type of parallel processing
similar MDMX system. The first widely deployed desktop SIMD was with Intel's MMX extensions to the x86 architecture in 1996. This sparked the introduction
Single instruction, multiple data
Single_instruction,_multiple_data
American drummer (born 1966)
Van Williams (born December 5, 1966) is an American musician, best known as the drummer of heavy metal band Nevermore. He hails from New York where he
Van_Williams_(drummer)
Design flaw in 1993-1997 Intel processors
and present in CPUs based on it, including the original Pentium, Pentium MMX, and Pentium OverDrive. Discovered in 1997, it can result in the processor
Pentium_F00F_bug
Microprocessor
(6x86MX) was first announced to be in development in mid 1996. It would have MMX and 32-bit optimization. The M2 would also have some of the same features
Cyrix_6x86
1996 video game
of Intel's then-new MMX technology, which facilitated better performance of full motion video playback. The game's engine used MMX-enhanced Indeo Video
Eraser:_Turnabout
Central computer component that executes instructions
superseded MMX in Intel's general-purpose processors, later IA-32 designs still support MMX. This is usually done by providing most of the MMX functionality
Central_processing_unit
Natural satellites of the planet Mars
original on 1 October 2021. Retrieved 3 September 2020. "MMX - Martian Moons eXploration". MMX at JAXA. "JAXA plans probe to bring back samples from moons
Moons_of_Mars
First-person shooter game
their upcoming MMX instruction set. Sweeney was immediately excited by the possibilities MMX presented, and put together a working MMX version of the
Unreal_(1998_video_game)
de la mission MMX baptisé IDEFIX® !". Mmx (in French). 2023-07-03. Retrieved 2023-07-18. Andrew Jones (2024-01-04). "Japan delays MMX Mars moon sample-return
Patrick_Michel
Microprocessor series by AMD
3DNow+) which added 5 new DSP instructions, but not the 19 new extended MMX instructions. The original K6-2 had a 64 KB primary cache and a much larger
AMD_K6-III
Brand of microprocessors by AMD
renamed "Enhanced 3DNow!" Additions included DSP instructions and the extended MMX subset of Intel SSE. Specifications L1-cache: 64 + 64 KB (data + instructions)
Athlon
Intel for use with their mobile processors, including the Pentium, Pentium MMX, Pentium II, Pentium III, and Celeron processors. The series consists of
Mobile_Module_Connector
Series of budget AMD microprocessors for personal computers
iGPUs. Socket FM2 CPU: Two or four Piledriver-cores GPU TeraScale 3 (VLIW4) MMX, SSE(1, 2, 3, S3, 4a, 4.1, 4.2), AMD64, AMD-V, AES, AVX, XOP, FMA(4, 3),
Athlon_X4
Mars mission to collect rock and dust samples
launch Mars-Grunt in the 2030s. A JAXA proposal, Martian Moons eXploration (MMX) is aimed at returning samples from Phobos. The NASA-ESA Mars Sample Return
Mars_sample-return_mission
64-bit extension of x86 architecture
mode. While registers for older floating-point implementations—the x87 and MMX—are still available, they are generally superseded by 128-bit vector registers
X86-64
Family of central processing unit models
DDR2-1066 MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, Cool'n'Quiet, NX bit, AMD-V
Athlon_II
Intel processor family
on most of these processors unless noted otherwise. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology
Intel Sandy Bridge-based Xeon microprocessors
Intel_Sandy_Bridge-based_Xeon_microprocessors
Chipset designed by Intel
Intel, supporting Socket 7 processors, including the Pentium and Pentium MMX. It is also known as i430HX and it was released in February 1996. The official
Intel_430HX
CPU by AMD
Family 5, Model 8, Stepping 0 L1-Cache: 32 + 32 KiB (Data + Instructions) MMX, 3DNow! 9.3 million transistors Super Socket 7 Front-side bus: 66, 100 MHz
AMD_K6-2
English dubstep musician
album in 2009. The second album, II – MMX, was released in 2010. Umile, Dominic (11 May 2010). "Clubroot: II - MMX". PopMatters. Archived from the original
Clubroot_(musician)
1995 Microsoft operating system version
Retrieved September 9, 2009. "GP Fault or Fatal Exception Error on Intel MMX CPU". Archived from the original on September 4, 2014. Retrieved June 9,
Windows_95
Commercial product for developing code
SYBASE INC. ANNOUNCES WATCOM C/C++ VERSION 11.0 Includes New Support For MMX Technology and Improved C++ language Support End of Life Notice for Watcom
Watcom_C/C++
This mission is called Martian Moons eXploration (MMX) and is a flagship Strategic Large Mission. MMX will build on the expertise the Japan Aerospace Exploration
List_of_missions_to_Mars
Physical and electrical specification for an x86-style CPU socket
the IDT WinChip, the Intel P5 Pentium (2.5–3.5 V, 75–200 MHz), the Pentium MMX (166–233 MHz), and the Rise Technology mP6. Socket 7 typically uses a 321-pin
Socket_7
models support: MMX All models support quad-processor configurations Steppings: B0, B1 Based on P6 microarchitecture All models support: MMX, SSE All models
List of Intel Xeon processors (P6-based)
List_of_Intel_Xeon_processors_(P6-based)
travel, tourism, insurance
MMX
MMX
MMX
MMX
MMX
MMX
MMX
MMX
MMX
travel, tourism, insurance