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Means of packaging an integrated circuit
Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before
Wafer-level_packaging
Integrated circuit packaging technology
Fan-out wafer-level packaging (also known as wafer-level fan-out packaging, fan-out WLP, FOWL packaging, FO-WLP, FOWLP, etc.) is an integrated circuit
Fan-out_wafer-level_packaging
Integrated circuit package that is no or barely larger than the die it contains
ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size
Chip-scale_package
Packaging technology for integrated circuits
Embedded wafer level ball grid array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made
Embedded wafer level ball grid array
Embedded_wafer_level_ball_grid_array
Aims to overcome limitations of semiconductors
packaging includes multi-chip modules, 3D ICs, 2.5D ICs, heterogeneous integration, fan-out wafer-level packaging, system-in-package, quilt packaging
Advanced packaging (semiconductors)
Advanced_packaging_(semiconductors)
Moroccan high-tech manufacturing company
customized wafer-level cameras for portable applications. It provides customized design and manufacturing services of wafer-level packaging, wafer-level optics
Nemotek_Technologie
circuit wafer – a disk of semiconductor material (usually silicon) on which electronic circuitry can be fabricated wafer-level packaging (WLP) – packaging ICs
Glossary of microelectronics manufacturing terms
Glossary_of_microelectronics_manufacturing_terms
American semiconductor equipment company
(interconnects). The company also builds equipment for back-end wafer-level packaging (WLP) and for related manufacturing markets such as for microelectromechanical
Lam_Research
Taiwanese manufacturer of semiconductor testing products
The packaging services include fan-out wafer-level packaging (FO-WLP), wafer-level chip-scale packaging (WL-CSP), flip chip, 2.5D and 3D packaging, system
ASE_Group
(2008). "Wafer Level Packaging: Balancing Device Requirements and Materials Properties" (PDF). IMAPS. International Microelectronics and Packaging Society
Thermocompression_bonding
System of building very large integrated circuit networks
are placed into packaging and re-tested for any damage that might occur during the packaging process. Flaws on the surface of the wafers and problems during
Wafer-scale_integration
Compounds in the Success of Fan-Out Wafer-Level Packaging Technology". Advances in Embedded and Fan-Out Wafer-Level Packaging Technologies. Hoboken, NJ, USA:
Epoxy_molding_compounds
Integrated circuit composed of several vertically stacked chips
integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs
Three-dimensional integrated circuit
Three-dimensional_integrated_circuit
American semiconductor company
semiconductor packaging called "Edge Protection". Companies portal Semiconductor industry Integrated circuit packaging Wafer-level packaging System in a package "Giel
Amkor_Technology
packaged using wafer level packaging. Large monolithic RF MEMS filters, phase shifters, and tunable matching networks require single chip packaging.
Radio-frequency microelectromechanical system
Radio-frequency_microelectromechanical_system
Chinese semiconductor company
Semiconductor industry in China Integrated circuit packaging Wafer-level packaging System in a package "2023 Annual Report" (PDF). Sina. "Changjiang Electronics
JCET_(company)
American electronics engineer
electronics engineer specializing in electronic packaging, and especially wafer-level packaging. She is head of Packaging & Systems Technology for Intel, and president
Beth_Keser
Thin slice of semiconductor used for the fabrication of integrated circuits
microcircuits are separated by wafer dicing and packaged as an integrated circuit. In the semiconductor industry, the term wafer appeared in the 1950s to describe
Wafer_(electronics)
electronics package dimensions Redistribution layer Small-outline transistor Wafer-level packaging "CPU Collection Museum - Chip Package Information"
List of electronic component packaging types
List_of_electronic_component_packaging_types
Type of synchronous graphics random-access memory
per package capacity from 16 Gb to 32 Gb Double the I/O pins from 32 to 64 36% lower thickness (0.7 mm down from 1.1 mm by using Fan-Out Wafer-Level Packaging
GDDR6_SDRAM
American semiconductor company
of trading. Wafer-scale integration – System of building very large integrated circuit networks Wafer-level packaging – Means of packaging an integrated
Cerebras_Systems
Highly anisotropic etch process
recently for creating through-silicon vias (TSVs) in advanced 3D wafer level packaging technology. In DRIE, the substrate is placed inside a reactor, and
Deep_reactive-ion_etching
Packaging technology
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS)
Wafer_bonding
Electronic component
SiP solutions may require multiple packaging technologies, such as flip chip, wire bonding, wafer-level packaging, through-silicon vias (TSVs), chiplets
System_in_a_package
History of semiconductor light source
manufacturing infrastructure. It allows for the wafer-level packaging of LED dies resulting in extremely small LED packages. GaN is often deposited using metalorganic
History_of_the_LED
Small lens, generally with a diameter less than a millimetre
methodology can now be used to fabricate wafer-level optical elements in a chip scale package. The result is a wafer-level camera module that measures .575 mm
Microlens
ISBN 3-18-343602-7. Farrens, S. (2008). "Metal Based Wafer Level Packaging". Global SMT & Packaging. Weldon, M. K.; Marsico, V. E.; Chabal, Y. J.; Hamann
Wafer_bond_characterization
Layer used to relocate a microchip's contacts
Engineering. J. H. Lau (2019). Redistribution-Layers for Fan-Out Wafer-Level Packaging and Heterogeneous Integrations. 2019 China Semiconductor Technology
Redistribution_layer
Organosulfur chemical compound used as a solvent
photoresist in TFT-LCD 'flat panel' displays and advanced packaging applications (such as wafer-level packaging / solder bump patterning). DMSO is also an excellent
Dimethyl_sulfoxide
Wafer bonding technique
Noeth, N.; Boisen, A.; Barniol, N. (2010). "Novel SU-8 based vacuum wafer-level packaging for MEMS devices". Microelectronic Engineering. 87 (5–8): 1173–1176
Adhesive bonding of semiconductor wafers
Adhesive_bonding_of_semiconductor_wafers
Electrical connection
Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D wafer-level packaging (WLP) solution in 2000. CMOS image sensors utilising TSV were commercialized
Through-silicon_via
Japanese semiconductor equipment manufacturer
Singapore. The lab is focused on the research and development of Wafer Level Packaging and assembly, to address the need of Internet of Things with devices
Tokyo_Electron
Technique that flips a microchip upside down to connect it
com. Archived from the original on 2014-10-16. "Wafer Level Chip Scale Package by the Wafer Level Package Development Team" (PDF). Analog Devices. Archived
Flip_chip
Defunct American semiconductor company
invest $60 million in Deca and will license Deca’s M-Series fan-out wafer-level packaging (FOWLP) technologies and processes. As part of the agreement, ASE
Cypress_Semiconductor
Electrical equipment manufacturing company
connectors, electron wires, sensors, electronic thermal components, wafer-level packaging Automotive segment Wire harnesses and other electrical components
Fujikura
Manufacturing process used to create integrated circuits
a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging. Within fabrication
Semiconductor device fabrication
Semiconductor_device_fabrication
(2008). "Wafer Level Packaging: Balancing Device Requirements and Materials Properties". IMAPS. International Microelectronics and Packaging Society.
Anodic_bonding
Topics referred to by the same term
circuit packaging, final stage in construction of an integrated circuit Quilt packaging, an integrated circuit packaging Wafer-level packaging, packaging an
Packaging_(disambiguation)
Digital electronic term
algorithm — FAN-out oriented test generation algorithm Fan-out wafer-level packaging Hamming weight Miles Murdocca, Apostolos Gerasoulis, and Saul Levy
Fan-out
Semiconductors trade show held in Taipei, Taiwan
collaboration, and business matching on key topics like 3D ICs, Fan-out wafer-level packaging, silicon photonics, and memory innovation. Also, Country Pavilion
Semicon_Taiwan
American manufacturing company
global ALD market. Advanced packaging systems include: Lithography tools used for copper pillar, fan-out wafer-level packaging (FOWLP) through-silicon via
Veeco
Multiple electronic componets in a single package
Typical packages for integrated passives are SIL (Standard In Line), SIP or any other packages (like DIL, DIP, QFN, chip-scale package/CSP, wafer level package/WLP
Integrated_passive_devices
advanced IC packaging, where it enables the processing of glass wafers and panels with through-glass vias (TGVs) for semiconductor packaging and MEMS devices
Laser_Induced_Deep_Etching
according to the used material, the production volume and the size of the wafers used for the fabrication. The attribute type is for Integrated Device Manufacturer
List_of_MEMS_foundries
Class of devices for nanoscale functionality
Springer. pp. 203–228. ISBN 978-0-387-26883-5. Pieters, P. (2005). "Wafer level packaging of micro/nanosystems". 5th IEEE Conference on Nanotechnology. IEEE
Nanoelectromechanical_systems
Type of thermal sensor
especially from moisture, TMOS sensor are packaged under vacuum. The wafer-level production enables also wafer-level packaging, allowing the possibility to integrate
T-MOS_thermal_sensor
Japanese explosives manufacturing company
semiconductor packaging, temporary and permanent photo patternable resists, and specialty polymer coating materials used in wafer-level packaging, MEMS fabrication
Nippon_Kayaku
American semiconductor company
specialized process tools are required before the wafer moves to a final packaging facility. The focus of packaging and assembly is to ensure an electrical connection
Onto_Innovation
German manufacturer of semiconductor products
Euro turnover Acquisition of Eurasem (Packaging, NL) and SMI (MEMS, USA) 2002 - TS16949 2005 - Opened 8" wafer fab in Duisburg as second production line
Elmos_Semiconductor
Topics referred to by the same term
several things, such as the following: Wafer-level packaging, a type of integrated circuit (microchip) packaging Weakest liberal precondition, a computer
WLP
Interface between an electronic test system and a semiconductor wafer
circuits on the wafer, thereby permitting the testing and validation of the circuits at the wafer level, usually before they are diced and packaged. It normally
Probe_card
(2008). "Wafer Level Packaging: Balancing Device Requirements and Materials Properties". IMAPS. International Microelectronics and Packaging Society.
Eutectic_bonding
Semiconductor device manufacturer
1996. It is now[when?] being shut down. The site also has a "Wafer Level Chip Scale Packaging" accreditation for eSIM ICs. In 1988, a small group of employees
STMicroelectronics
Chocolate bar made by Ferrero
wafer confection made by Italian confectionery maker Ferrero. Part of the Kinder Chocolate brand line, Kinder Bueno is a hazelnut-cream-filled wafer covered
Kinder_Bueno
Wafer bonding process in semiconductor production
Direct bonding, or fusion bonding, is a wafer bonding process without any additional intermediate layers. It is based on chemical bonds between two surfaces
Direct_bonding
Semiconductor memory supply crisis
requiring approximately 900,000 wafers per month. The deal involved the supply of undiced wafers rather than packaged chips to streamline logistics for
2025–present global memory supply shortage
2025–present_global_memory_supply_shortage
Thermocompression bonding Measurement and characterization for wafer level packaging technologies Reactive materials NanoFoil Böttge, B. and Bräuer,
Reactive_bonding
Electronic circuit formed on a small, flat piece of semiconductor material
is tested before packaging using automated test equipment (ATE), in a procedure known as wafer testing or wafer probing. The wafer is then cut into rectangular
Integrated_circuit
American electronic engineer
scaling superconducting quantum hardware through wafer-level microfabrication and advanced packaging". She became a Distinguished Engineer at IBM, before
Christy_Tyberg
Wafer bond with glass central layer
(2005). "Glass frit bonding: an universal technology for wafer level encapsulation and packaging". Microsystem Technologies. 12 (1–2): 63–68. doi:10
Glass_frit_bonding
Topics referred to by the same term
Jimmy Neutron movie and series Fan-out wafer-level packaging or FOWL packaging, an integrated circuits packaging technology Fowl River, a river in Alabama
Fowl_(disambiguation)
Chinese Semiconductor Company
company headquartered in Shaoxing, Zhejiang. It provides wafer foundry and module packaging solutions. On 9 March 2018, the company was founded as a joint
United_Nova_Technology
Chocolate cookie with creme filling made by Nabisco
Daimler AG. Their packaging in the 1990s consisted of a "miniaturized" version of the full-sized cardboard tray and box used in Oreo packaging at the time.
Oreo
Taiwanese semiconductor foundry company
TSMC has a global capacity of about thirteen million 300 mm-equivalent wafers per year as of 2020 and produces chips for customers with process nodes
TSMC
activation on clean wafer surfaces. Further, the increase is caused by elevation in amount of Si-OH groups, removal of contaminants on the wafer surface, the
Plasma-activated_bonding
Device consisting of piezoelectric material
parts like basic resonators and filters are packaged in miniaturised/small form factor like wafer level packages. FBARs can also be integrated with power
Thin-film bulk acoustic resonator
Thin-film_bulk_acoustic_resonator
Part of manufacturing process used to create integrated circuits
deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. For
Back_end_of_line
United States defense standard
measurement for digital microcircuits 5013 Wafer fabrication control and wafer acceptance procedures for processed GaAs wafers "Mil-Std-883F, Department of Defense
MIL-STD-883
American technology company
wafer-level architectures in 2000 with the development of FlipFET wafer packaging. In 2002, it introduced DirectFET, a proprietary MOSFET packaging technology
International_Rectifier
IBM hybrid circuit technology introduced in 1964
Device (ULD) use flat-pack ceramic packages, much smaller than SLT's metal cans. Each package contains a ceramic wafer with up to four silicon dies on top
Solid_Logic_Technology
1990s packaging consisted of a "miniaturized" version of the full-size cardboard tray and box used in packaging at the time. Their current packaging consists
List_of_Oreo_varieties
Method of circuit board manufacture
effectively merges two levels of electronic packaging: level 1 (components) and level 2 (wiring boards), and may be referred to as "level 1.5". A finished semiconductor
Chip_on_board
Integrated circuit customized for a specific task
performance as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% circuit utilization. Often difficulties in routing the
Application-specific integrated circuit
Application-specific_integrated_circuit
Timing oscillator
chip-level vacuum chambers, are diced from their silicon wafers, and the resonator die are stacked on CMOS die and molded into plastic packages to form
Microelectromechanical system oscillator
Microelectromechanical_system_oscillator
Surface-mount packaging that uses an array of solder balls
Small-outline integrated circuit (SOIC) Chip carrier: chip packaging and package types list Embedded wafer level ball grid array "Soldering 101 - A Basic Overview"
Ball_grid_array
wire bond and package the device before testing. Micromanipulator 200L Semiautomatic Probe Station with Pattern recognition software & wafer being observed
Mechanical_probe_station
automatically testing and diagnosing faults in sophisticated electronic packaged parts or on wafer testing, including system on chips and integrated circuits. ATE
Automatic_test_equipment
American electronics company
had a full array of divisions including Design, Photomask, Wafer Fab, Test, Assembly/Packaging, Product Engineering, Quality/Reliability, Sales/Marketing
Mostek
microelectromechanical systems (MEMS) integration and packaging applications. OSTE is suitable for heterogeneous silicon wafer level integration depending on its application
Off-stoichiometry thiol-ene polymer
Off-stoichiometry_thiol-ene_polymer
Material of moderate electrical conductivity
wafers. The round shape characteristic of these wafers comes from single-crystal ingots usually produced using the Czochralski method. Silicon wafers
Semiconductor
Type of memory used on processors that require high transfer rate memory
(Samsung) (January 2017). "A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution"
High_Bandwidth_Memory
British semiconductor company
metal-oxide-semiconductor field-effect transistor (MOSFET), such as silicon wafers, where the semiconductor material typically is the substrate. Silicon semiconductor
Pragmatic_Semiconductor
Semiconductor foundry company
Singapore, the European Union, and the United States: one 200 mm and one 300 mm wafer fabrication plant in Singapore; one 300 mm plant in Dresden, Germany; one
GlobalFoundries
Advanced Packaging. 29 (2): 218–226. doi:10.1109/TADVP.2006.873138. ISSN 1521-3323. S2CID 27663896. R. Kondou and T. Suga, "Room temperature SiO2 wafer bonding
Surface_activated_bonding
Type of semiconductor laser diode
which emit from surfaces formed by cleaving the individual chip out of a wafer. VCSELs are used in various laser products, including computer mice, fiber-optic
Vertical-cavity surface-emitting laser
Vertical-cavity_surface-emitting_laser
High purity form of silicon
ingots which are large square blocks weighing around 800 kg for making solar wafers or submitted as-is to a recrystallization process to grow single crystal
Polycrystalline_silicon
Formal testing of packaging
Package testing or packaging testing involves the measurement of a characteristic or property involved with packaging. This includes packaging materials
Package_testing
Lithography that does not use photomasks
focal-spot write the image pattern onto a chemical resist-coated substrate (e.g. wafer) by means of UV radiation or electron beam. In microlithography, typically
Maskless_lithography
Electronic component that exploits the electronic properties of semiconductor materials
a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging. Within fabrication
Semiconductor_device
non-functional, the entire wafer would have to be discarded. The chance this would happen would approach 100% at the complexity levels involved. As with other
Trilogy_Systems
Chinese Semiconductor company
Wafer-level optical elements are fabricated in a single step by combining CMOS image sensors, chip scale packaging processes, (CSP) and wafer-level optics
OmniVision_Technologies
Intel microprocessor series released in 2023
Intel 4 wafers took place at Intel's D1D fabrication facility in Hillsboro, Oregon. The D1D fabrication facility has a total output of 40,000 wafers a month
Meteor_Lake
Chocolate bar
introduced by British company Rowntree's in 1976. It consists of a filled wafer with caramel and cereals covered in milk chocolate. Lion was first launched
Lion_(chocolate_bar)
American computer memory manufacturer
moved from consulting to manufacturing with the completion of its first wafer fabrication unit ("Fab 1"), producing 64K DRAM chips. In 1984, the company
Micron_Technology
American technology company
LitePoint, Teradyne's product portfolio stretched from wafer test of semiconductor chips to system-level circuit boards to products ready for store shelves
Teradyne
Photolithographic Tool
A stepper or wafer stepper is a device used in the manufacture of integrated circuits (ICs). It is an essential part of the process of photolithography
Stepper
2006–2011 German computer memory manufacturer
previous 90 nm technology thereby increasing potential chip output per wafer by about 40 percent. On November 1, 2007, Qimonda AG announced shipment
Qimonda
Joining technique used in manufacture and repair
Wiemer, M.; Jia, C.; Töpper, M.; Hauck, K. (2006). "Wafer Bonding with BCB and SU-8 for MEMS Packaging". 2006 1st Electronic Systemintegration Technology
Adhesive_bonding
Thinly sliced potatoes, deep-fried or baked
shelf-life of packaged potato chips". Packag. Technol. Sci. 7 (2): 81–85. doi:10.1002/pts.2770070205. ISSN 0894-3214. M.A. Del Nobile (2001). "Packaging design
Potato_chips
GPU microarchitecture by AMD
monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer. Alternatively, a large monolithic RDNA 3 die
RDNA_3
WAFER LEVEL-PACKAGING
WAFER LEVEL-PACKAGING
Surname or Lastname
English (of Norman origin)
English (of Norman origin) : nickname for a fleet-footed or timid person, from Old French levre ‘hare’ (Latin lepus, genitive leporis). It may also have been a metonymic occupational name for a hunter of hares.English (of Norman origin) : topographic name for someone who lived in a place thickly grown with rushes, from Old English lǣfer ‘rush’, ‘reed’, ‘iris’. Compare Laver 3. Great and Little Lever in Greater Manchester (formerly in Lancashire) are named with this word (in a collective sense) and in some cases the surname may also be derived from these places.English (of Norman origin) : possibly from an unrecorded Middle English survival of an Old English personal name, Lēofhere, composed of the elements lēof ‘dear’, ‘beloved’ + here ‘army’.
Surname or Lastname
Jewish
Jewish : variant spelling of Levy.English : variant spelling of Leavey.
Boy/Male
Hebrew
United.
Surname or Lastname
Jewish (Ashkenazic)
Jewish (Ashkenazic) : variant spelling of Levin.English, North German, and Dutch : from the Germanic personal name represented by Old English Lēofwine, Saxon Liafwin, composed of the elements lēof ‘dear’, ‘beloved’ + wine ‘friend’.English and Scottish : habitational name from places called Leven in East Yorkshire, Fife, and Renfrew. The first is probably from a stream name, possibly derived from a Celtic word meaning smooth (as in Welsh llyfyn). The Scottish place name is from a Gaelic river name meaning ‘elm river’.Dutch and North German : from a Flemish saint’s name, Lefwin (Lieven), the patron saint of Ghent (see Lewin 2).
Male
English
Variant spelling of English Lovell, LOVEL means "little wolf."
Male
Yiddish
(לֶעמְל) Yiddish name LEMEL means "little lamb; meek."
Boy/Male
Australian, German, Turkish
Victory
Surname or Lastname
English
English : variant of Walter, representing the normal medieval pronunciation of the name.English and German (Rhineland) : topographic name for someone who lived by a stretch of water, Middle English, Low German water.Irish : adopted as an English translation of Gaelic Ó Fuartháin (see Foran), being wrongly taken as Ó Fuaruisce ‘son of cold water’.
Boy/Male
Shakespearean
King Richard III' Lord Lovel.
Surname or Lastname
English
English : nickname for a watchful person, from Middle English waker ‘watchful’, ‘vigilant’.
Boy/Male
Yiddish
Dearly loved.
Surname or Lastname
English
English : from Anglo-Norman French wafre ‘wafer’, alternating with wafrer, wafrour ‘waferer’, an occupational name for a maker or seller of eucharistic wafers or thin cakes.English : from an Old German personal name Waifar, Waifer, Old French Gaifier.
Surname or Lastname
English
English : variant spelling of Lovell.
Boy/Male
Indian, Tamil
High Level
Surname or Lastname
English
English : variant of Bevill.
Surname or Lastname
English
English : from a late Old English personal name Lēofweald, composed of the elements lēof ‘dear’, ‘beloved’ + weald ‘power’, ‘rule’.French : variant spelling of Level.
Boy/Male
Scandinavian
Wolf counsel.
Surname or Lastname
English
English : variant spelling of Revell.French : habitational name from any of the places so named, for example in Isère and Haute-Garonne.French and southern French : nickname from Old French, Occitan reveau ‘rebel’.
Surname or Lastname
English
English : unexplained.German (also Wäger), Swiss German, and Jewish (Ashkenazic) : from Middle High German wæger ‘weigher’, German Waager, an occupational name for an official responsible for weighing produce, especially produce offered as rent in kind, or for an official in charge of checking weights and measures used by merchants.
Boy/Male
Hindu, Indian
Plenty
WAFER LEVEL-PACKAGING
WAFER LEVEL-PACKAGING
Boy/Male
Indian, Punjabi, Sikh
Attractive Like the Moon
Boy/Male
Indian
A wish, Desire
Boy/Male
Arabic, Muslim
Two Friends of Prophet Muhammad; Shepherd
Boy/Male
Arabic, Muslim
Servant of the Originator
Boy/Male
Bengali, Hindu, Indian, Traditional
Servant of the God
Surname or Lastname
English
English : variant of Hill, from southeastern Middle English hell ‘hill’, a dialect form characteristic of Kent and Sussex.English : from a personal name, Helle, which may have been a variant of Elie (a Middle English form of Elias), or perhaps a short form of a personal name formed with Hild- as the first element (see Hilliard for example), or perhaps from the female personal name Helen.German : nickname from Middle High German hell ‘bright’, ‘shining’.German : variant of Helle 3.
Girl/Female
Muslim/Islamic
Entertaining female companion
Girl/Female
Biblical
Point, joy of tenderness.
Boy/Male
Hindu, Indian
Lord Vishnu; Husband of Tulsi (Plant)
Boy/Male
Arabic, Muslim
Justice; Righteous
WAFER LEVEL-PACKAGING
WAFER LEVEL-PACKAGING
WAFER LEVEL-PACKAGING
WAFER LEVEL-PACKAGING
WAFER LEVEL-PACKAGING
a.
Even; flat; having no part higher than another; having, or conforming to, the curvature which belongs to the undisturbed liquid parts of the earth's surface; as, a level field; level ground; the level surface of a pond or lake.
v. t.
To attend the levee or levees of.
n.
A line or surface to which, at every point, a vertical or plumb line is perpendicular; a line or surface which is everywhere parallel to the surface of still water; -- this is the true level, and is a curve or surface in which all points are equally distant from the center of the earth, or rather would be so if the earth were an exact sphere.
n.
A measurement of the difference of altitude of two points, by means of a level; as, to take a level.
a.
Well balanced; even; just; steady; impartial; as, a level head; a level understanding. [Colloq.]
v. t.
To bring to a lower level; to overthrow; to topple down; to reduce to a flat surface; to lower.
v. i.
To be level; to be on a level with, or on an equality with, something; hence, to accord; to agree; to suit.
a.
Having the slant of a bevel; slanting.
v. t.
Figuratively, to bring to a common level or plane, in respect of rank, condition, character, privilege, etc.; as, to level all the ranks and conditions of men.
n.
An approximately horizontal line or surface at a certain degree of altitude, or distance from the center of the earth; as, to climb from the level of the coast to the level of the plateau and then descend to the level of the valley or of the sea.
a.
Coinciding or parallel with the plane of the horizon; horizontal; as, the telescope is now level.
v. t.
To make level; to make horizontal; to bring to the condition of a level line or surface; hence, to make flat or even; as, to level a road, a walk, or a garden.
n.
A horizontal line or plane; that is, a straight line or a plane which is tangent to a true level at a given point and hence parallel to the horizon at that point; -- this is the apparent level at the given point.
n.
A uniform or average height; a normal plane or altitude; a condition conformable to natural law or which will secure a level surface; as, moving fluids seek a level.
v. t.
To adjust or adapt to a certain level; as, to level remarks to the capacity of children.